Transcription
Hey friends, welcome to the YouTube channel ALL ABOUT ELECTRONICS. So in this video, we will learn about the Sample and Hold circuit.
So in this video, we will see the basic circuit of the Sample and Hold. And then after, we will also understand the different specifications of the Sample and Hold. So, if we know these specifications, then we can easily choose the proper Sample and Hold circuit for the specific application.
Alright, so we know that this Sample and Hold is a very integral part of any analog to digital conversion. So, in the earlier videos of the ADC, we have seen that for the analog to digital conversion, first the analog signal is sampled at the fixed intervals using this Sample and Hold circuit. So, this sampled signal is then given to the ADC, and this ADC then performs the quantization. And based on the quantization, this ADC encodes each sample in the digital form. That means the first step in any analog to digital conversion is the sampling. And this sampling is performed using the Sample and Hold circuit.
So this Sample and Hold circuit has the two inputs. One is the analog input, where the analog signal is applied. And the second one is the control input, where the Sample and Hold commands are given. So when the Sample command is given, then the Sample and Hold circuit samples the input signal. Or we can say that it is tracking the input signal. And whenever the Hold command is given, then it holds the last sample value of the analog signal during the tracking.
So as you can see in this picture, the train of Sample and Hold commands are given to the Sample and Hold circuit. So as you can see, when the Sample command is given, at that time, it is tracing the input signal. And as soon as we provide the Hold command, then it is holding the last sample value. So during this Hold period, where the input remains flat, during that period, the ADC can perform the analog to digital conversion.
So for the ideal Sample and Hold circuit, if we apply the sine wave as an input, and at the same time, if we also apply the Sample and Hold commands as shown in the figure, then this is how the output will look like. That means this is the output of the Sample and Hold circuit.
So now, let's see the basic components of the Sample and Hold circuit. So the two key components of the Sample and Hold circuits are the switch and the Hold capacitor. So whenever the Sample command is given to the switch, then the switch remains in the closed condition. And at that time, this Hold capacitor follows the input signal. And ideally, the voltage across the capacitor should be same as the input signal. And now, when the Hold command is given, then the switch gets opened. And now, this Hold capacitor holds the last sample value during the tracking period. And during this Hold period, the ADC can perform the analog to digital conversion. So this switch operation can be implemented either using the BJT, JFET or the MOSFETs. But nowadays, mostly the MOSFET-based switches are commonly used. So that is the basic working principle of the Sample and Hold circuit.
So now, if we just use this simple circuit, then we might face the issue both on the input as well as the output side. For example, on the input side, how fast this Hold capacitor is able to track the input signal, that depends on the value of the Hold capacitor as well as the source impedance of the input signal. So basically, that depends on the RC time constant of the charging circuit. And with the fixed value of the Hold capacitor, that depends on the source impedance of the input signal. So for some input, if the source impedance is higher, then the RC time constant will increase. And in that case, during the sample mode, this Hold capacitor will not be able to track the input signal properly. That means in this case, how well the Sample and Hold is able to track the input signal, that depends on the source impedance of the input signal.
Similarly, during the Hold period, how well this capacitor is able to hold the charge, that depends on the value of this load resistance. Because during the Hold period, the charge across the capacitor will discharge through this path. So typically, here the load will be the input impedance of the ADC. And if that is not very high, then we might see the faster discharge of the capacitor. So ideally, the voltage across the Hold capacitor should remain constant during the Hold period. But because of the faster discharging of this capacitor, we will see the drop in the voltage across the capacitor. And this phenomenon is known as the droop. So we will discuss this phenomenon later on. But here, the thing is that this load impedance can affect the voltage across the capacitor during the Hold period.
So to remove that dependency, both on the input as well as the output side, typically, the input and output buffers are used. So as you can see, this input buffer is connected just before the switch, while the output buffer is connected after this Hold capacitor. And we know that the op-amp can be used as the buffer. So these buffers provide the high input impedance as well as the low output impedance. So on the input side, first, because of this buffer, there is no dependency on the source impedance. And the second thing is, since the output impedance of this buffer is very low, so now this RC time constant during the sampling mode will be very low.
Similarly, on the output side, because of this buffer, there is no dependency on the load resistance. And the second thing is, since the input impedance of the op-amp is very high, so it will hold the charge across the Hold capacitor for the longer time. So that is the typical circuit of the Sample and Hold. And this architecture, which is shown over here is the open-loop architecture. Because here, there is no feedback from the output to the input side. But similarly, some Sample and Hold circuits also use the closed-loop architecture. But here in this video, we will not discuss about the closed-loop architecture.
So now, let's see some of the basic specifications of the Sample and Hold circuit. So by knowing these specifications and the meaning of it, we can choose the right Sample and Hold for the specific application. So typically, the Sample and Hold specifications are categorized in the four parts. The first is when the circuit is in the Sample mode and the second is during the Sample to Hold mode transition. Similarly, the third type of specifications are defined for the Hold period. And similarly, some specifications are defined for the Hold to Sample mode transitions.
So first, let's see the Sample mode specifications. So one of the specifications for the Sample mode is the offset voltage. So typically, in this Sample and Hold, during the Sample mode, the output should follow the input signal, right? That means ideally, the output of this buffer should be same as the input signal. But sometimes, due to the offset errors of the op-amp, in the output, we might see some DC offset. So typically, it is mentioned in the specifications.
The second one is the gain error. So like I said, during the Sample mode, this Sample and Hold should track the input signal. So if we see the input-output transfer characteristic, then ideally, it should look like this. But sometimes, we might have a gain error. That means this Vout is k times the input signal, where this k can be greater than or less than 1. So this is another probable error during the sampling.
The third one is the slew rate. So it shows that how fast the output of the Sample and Hold can change. And typically, it is mentioned in the volt per microsecond. So this specification tells us that up to what frequency and what input range, the Sample and Hold is able to track the input signal correctly. And similarly, another specification that is mentioned during the Sample mode is the bandwidth. That is the bandwidth of the Sample and Hold circuit. So this specification also shows us the maximum signal frequency, which can be supported and tracked by the Sample and Hold circuit. But the only difference between this and the earlier specification is that, this specification is defined for the small signals. That means this specification is useful for the input signal, whose amplitude is very small. While the earlier specification or the slew rate is useful when we have a large voltage swing in the input signal. So of course, the slew rate defined bandwidth will always be lesser than this small signal bandwidth. But these two specifications tell us the maximum frequency, which can be tracked by this Sample and Hold circuit. And accordingly, we can choose the right Sample and Hold for the specific application. So these are the Sample mode specifications.
So now, similarly, let's see the specifications, which are defined for the Sample to Hold mode transition. So of course, when we apply the Hold command, then the Sample and Hold circuit will take some finite time to go from the Sample mode to the Hold mode. So these specifications are defined for the period when the Sample and Hold circuit is transitioning from the Sample mode to the Hold mode. So there are a couple of specifications and one of them is the Aperture time. So it shows the time between the application of the Hold command and when the input signal gets actually disconnected from the Hold capacitor. So ideally, when we apply the Hold command, then immediately, this switch should get open and this input signal should get disconnected from the Hold capacitor. But in reality, this switch takes some finite time for the opening. So this duration is referred as the Aperture time.
Then if we see the next important specification, then that is the Hold mode settling time. So it shows the time required for the output to settle within the specified error band once the Hold command is given. That means once we apply the Hold signal, then there will be a transient in the output before it gets settled to the intended value. So this time that is taken by the output to get settled in a specified error band is known as the Hold mode settling time. And generally, this error band is specified as the 1% or 0.1% or sometimes the half LSB of the full-scale voltage. That means once we apply the Hold command, then after the settling time only, the output of this Sample and hold will be stable. And after this time only, the ADC should start performing the conversion. So this specification is one of the important specifications for the ADC. And once again, we will talk about it at the later part of the video.
So then after, another important specification is the Hold step or the pedestal error. So this specification shows the additional voltage step that appears at the output due to this sample-to-hold transition. So basically, when the Hold command is given and when the switch gets opened at that time, there is a charge injection from the switch to the Hold capacitor. And because of this charge transfer, we will see some additional voltage at the output on top of the desired voltage. So this additional offset voltage at the output is known as the Hold step. And this error is also known as the pedestal error. So for example, in this case, ideally, once the Hold command is given, then this Hold capacitor should reach to this voltage. But here, because of the charge injection during the switching, we are getting this additional voltage. So this voltage is known as the Hold step. So this Hold step voltage can be given as Q divided by CH, where the Q is the amount of charge that is injected into the Hold capacitor, and the CH is the value of this Hold capacitor. So as you can see, if we choose the larger value of the Hold capacitor, then this Hold step will be lesser. But at the same time, now the sample and hold will not be able to track the input signal faster. So there is always a trade-off, and one should select the value of this Hold capacitor based on the application.
So we have seen that the one way of reducing the Hold step is by increasing the value of the Hold capacitor. But apart from that, there is another way also, we can also reduce the Hold step. So in this technique, typically a CMOS based transmission gate is used as a switch. Because we know that the CMOS switch consists of both NMOS as well as the PMOS transistors. So because of that, the effect of the charge injection will get nullified, or at least it is possible to minimize that effect. So in this way, by using these different techniques, it is possible to minimize this pedestal error. So these are the specifications for the sample to hold mode transition.
So similarly, now let's see the hold mode specifications. So these are the specifications where the switch is completely open and the hold capacitor is disconnected from the input side. So one such specification is the droop rate. And as we have seen earlier, it is the rate at which the output voltage is changing due to the leakage from the hold capacitor. So ideally during the hold period, after this hold mode settling time, the output across the capacitor should remain constant. But in reality, due to the leakage through the hold capacitor, we are seeing the change in this hold voltage. And this change in the voltage is known as the droop. And the rate at which this voltage is changing is known as the droop rate. So this leakage current through the hold capacitor consists of the three parts. The one reason is through the leakage through this hold capacitor. The second reason for this leakage current is the leakage through this analog switch. And the third reason is the input bias current of this output amplifier. So it is quite possible that the polarity of these currents may not be the same. But let's say the overall leakage current is equal to IL. So this current can be given as CH times dVH divided by dT, where the CH is the capacitance of this hold capacitor and this VH is the voltage across the hold capacitor. So this droop rate or this dVH divided by dt is equal to IL divided by CH. So as you can see, as we increase the value of this hold capacitor, then this droop rate will reduce. So while selecting the value of this hold capacitor, we should ensure that during the conversion time of the ADC or during this hold period, the change in the hold voltage should not be more than half LSB. And by ensuring that, we can get the desired accuracy during the conversion.
Then if we see the next hold mode specification, then that is the feed-through attenuation ratio. So it shows the fraction of the input signal that appears at the output during the hold mode. And typically, it is expressed in the dB. So basically, it shows the ability of the circuit to block the input signal when the circuit is in the hold mode. So ideally during the hold period, when the switch gets opened, then there should not be any connection between the input and the output, right? But many times, the parasitic capacitance exists between the input and the output side. And through this parasitic capacitance, there is a weak coupling of the input signal to the output side. And because of that, some fraction of the input signal is appearing at the output. So this parameter is typically defined at the specific frequency. And again, the value of this parameter should be less than the half LSB of the full-scale input voltage, so that it will not affect the accuracy of the conversion. So these are the hold mode specifications.
So now finally, let's see the specification which is defined for the hold mode to the sample mode transition. That means when the sample and hold circuit is going from the hold mode to the sample mode. So one such important specification is the acquisition time. So it shows the maximum time that is required to acquire the new input voltage once the sample command is given. So we know that once the hold command is given, then the sample and hold circuit try to keep the output voltage constant to the last sample value. Now during this hold period, if we see the input signal, then it is still changing, right? But here, the sample and hold circuit is not tracking it. But once we apply the sample signal again, then it starts tracking the input signal again. So ideally, it should reach to the input immediately. But in reality, it will take some finite time to reach to this new input level. So once the output of the sample and hold reaches within the specified error band around the input signal, then we can say that the signal is acquired. That means this time required by the sample and hold to reach there within the specified error band is known as this acquisition time. And obviously, the maximum acquisition time will occur when the hold capacitor needs to charge to the full-scale voltage range. So let's say, the full-scale voltage range for the some sample and hold is from -2V to +2V So for example, if the hold capacitor needs to go from the minus two volt to the plus two volt, then in that case, we will see the maximum acquisition time. So this acquisition time depends on the value of the hold capacitor. So for the faster acquisition time, the value of the hold capacitor should be small. But by choosing the small value of the hold capacitor, the droop rate will increase. So there is always a trade-off between the speed and the accuracy. And one should select the sample and hold circuit and the value of the hold capacitor according to the application.
So these are the different specifications of the sample and hold circuit. Now among these specifications, the two sample and hold specifications are very important for deciding the maximum sampling frequency. That is the maximum frequency at which the input signal can be sampled. So these two specifications are the acquisition time and the hold mode settling time. So these two times show the maximum time that is required by the sample and hold during the sampling and the holding period. And on top of that, we also have this ADC conversion time. So these three times show the minimum time that is required by the sample and hold circuit and the ADC to complete the one conversion. And if we see the maximum sampling frequency, then that is the inverse of that. So in this way, if we know the different specifications of the sample and hold, then we can easily choose the right sample and hold for the specific application.
So I hope in this video, you understood the basic circuit of the sample and hold. And I hope you also understood what are the different important specifications of the sample and hold. So if you have any question or suggestion, then do let me know here in the comment section below. If you like this video, hit the like button and subscribe to the channel for more such videos.