Transcription
Just like rock stars on tour, Moore's Law has been declared dead more than 20 times. And today, I'm here at Stanford, in the heart of Silicon Valley, where it all started, and Moore's Law is very much alive, as you will see.
Today, we already know how to get computer chips to 2nm and even beyond that. In this episode, we will take a bold look into the next 15 years in technology, how it will evolve step by step, what it means for key players like Google and NVIDIA, and what it means for you.
For the last 50 years, everything you use, your phone, your laptop, even AI like ChatGPT, has been powered by one tiny invention: the transistor. These nanoscopic switches turn on and off billions of times per second, and this is the main engine behind our entire digital world.
Have you ever noticed that every tech giant, like NVIDIA, Google, or Apple, is building their custom computer chips? And why? Because the real race is happening inside the chip. And if you're not watching this space closely, you are missing the bigger picture.
Just look at NVIDIA. Their current Blackwell GPU features 28 billion transistors, but with their upcoming Rubin platform, we are talking about 1.3 quadrillion transistors packed into a single server. And this is happening right now.
Here is what most people miss: while AI capabilities double roughly every 7 months, which gives us about 3.4 four times a year, the performance of the underlying hardware is only improving by 1.4 times a year. And that's the problem. Just think about this gap.
Now, to understand why, we have to look deeper. Because in fact, the advancements of computer chips are coming from many different levels, starting from device level, and then architecture level, where we can have new designs and implement new algorithms, and then the system level, including software stack and cooling. So, it all comes together here, but the foundation is still the transistor.
What's very interesting, most of us hear about TSMC, the giant that manufactures computer chips at scale. But behind the scenes, there is another key innovator: IMEC. IMEC invents new technologies, including transistor technologies, and then TSMC is building them for the world.
Now, IMEC just released their new internal roadmap that lays out close to the next two decades in technology, and I got a chance to talk directly to the team behind these innovations, and I will unpack all of this for you today. And unlike other tech channels that just report on news, I'm actually coming from a chip design background. I spent a decade building these technologies, so this channel is the best place to learn about it. Make sure to subscribe not to miss what is next in technology.
Well, this is a very exciting roadmap. It shows step by step how we are going to scale from today's 2nm down to an astonishing 0.2nm by 2037, and even beyond that by 2039. What's fascinating, it's not just about transistors. It also touches upon all the parts of the ecosystem, including tools and materials we will have to adapt along the way.
Right now, as of 2025, we are at the 2nm generation and right in the middle of transition from FinFET to the next big thing. If we take any modern chip, like AMD GPU or Apple Silicon, they're still built using FinFET technology.
Now, if you look back in time, all the way back when I was at university, these were easy days, because back then we were using planar transistors, simple, straightforward 2D structures on silicon. A transistor is basically a tiny switch, and the gate controls it. So, when we apply a certain voltage to the gate, it turns on, and the current flows from the source to the drain. And then, from year to year, we kept shrinking transistors, especially the channel, the part where the current flows. And soon, we started running into big problems.
At some point, the good old planar transistor could not keep up anymore, and we had to flip the entire structure. Instead of keeping the structure flat, engineers raised the channel up as a vertical fin. Imagine it like a shark fin sticking out of water. It actually resembles a fish fin, that's why it's called FinFET. In fact, when I first joined the industry, we were right in the middle of this transition from planar devices to FinFET, and this was a huge shift. It was a huge shift because in transistors, what really counts is how well you can control the current in the channel, how cleanly you can switch it on and off. And these new devices gave us much better control, and also let us fit more transistors in the same space. And back then, everyone was a huge fan of FinFET. Everyone was talking about it.
But you know, every device, every architecture serves us for several generations until it hits a limit. You know, just as a fastest runner at some point will hit a physical limit. And this is a time when we are actually right now. And this is a time for entirely new technology. And this is going to be one of the biggest shifts in history.
It turns out, even transistors need to relax. So, we laid the fin down and stacked several of them like floors, one on top of the other. This new design is called Gate-All-Around or nanosheet. Different fabs have different names, but the idea is the same. What's exciting, this technology is arriving very soon. TSMC is bringing it first to AMD and Apple chips by the end of this year.
The genius idea behind this device is that by laying the fin on its side, we gain now access to all four sides of the channel. You know, in FinFETs, the gate wraps around three sides. Now, with this new device, the gate is wrapped around all four. And that extra contact allows us to better control it, even at smaller scales.
Well, this new device comes with a whole set of new manufacturing challenges. The biggest challenge is that you cannot see the underside of the nanosheets directly. And for these steps, Applied Materials and ASM own the secret sauce. I covered it in the previous episodes on this channel. I will drop some links in the description box below.
Good news: this challenge is solved. And this allowed us to shrink beyond 3nm. Just to give you a sense of what is enabling, for example, TSMC in N3 process node was able to pack 200 million transistors per square millimeter. And now, with N2, with 2nm, they are able to pack 300 million transistors per square millimeter. That's mind-blowing.
However, the most exciting part about this new technology is not just the new transistor shape. As you can see on the roadmap, it introduces something that has never been done before: backside power delivery. Just imagine, until now, all the wires for power and signaling have been crammed on top of the chip. You can imagine it like trying to bring all the plumbing and electricity through the ceiling. As you can imagine, it gets messy and it takes up a lot of space. And backside power delivery just flips that. Imagine taking all the power signaling from the top and bringing it to the backside, to the floor, so you can free up a lot of space on the top for signaling, for interconnecting the logic gates that are actually doing the computing.
This is a genius idea, but very hard to do in practice because it requires a total redesign of how chips are powered. And right now, companies like TSMC and Intel are racing to bring this new architecture and this new power delivery to the market. And from next year on, this new technology is going to power everything from your phone to the most advanced AI on Earth.
Now, we know, just like with any other technology, at some point it won't scale anymore. And according to the IMEC roadmap, it will happen at around 1nm. Or here, we are typically switching to Ångström dimensions, which means we are likely to hit the wall with this one at roughly 10 Ångströms. You know, old ways won't bring you to new places. So, here we will likely have to reinvent the device once again. You know, just like in your life, you can't do the same thing over and over again and expect a better outcome. You have to constantly reinvent yourself. Think what is next.
Just like me at Stanford Business School, right now I'm overwhelmed, but in the best way possible. According to the roadmap, they're projecting that the next big thing is going to be CFET architecture. Try to imagine what would happen if we take the Gate-All-Around device we've just discussed and then pile them one on top of the other. Now, finally, we're starting to grow vertically, just like the skyscrapers behind the camera in San Francisco. And it's intuitive, right? If we want to reduce the footprint. And this idea have been around for a while, but it takes a lot of time to figure out the recipe. And now, it's not just about figuring out the backside power delivery, it's also now about bringing in the signal for this bottom device.
Now, if we can manage to do that, and I'm pretty sure we will, this will unlock the next level, which will allow us to scale to single Ångström dimensions. Just think about it. This is mind-blowing.
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Now, we approaching the most exciting part of this video. Now, we will discuss the breakthrough materials and tools that will define the next two decades in technology. Let's start with lithography, or how we call it in the industry, litho. So, imagine as transistors are becoming smaller and smaller, the little metal wires, the interconnects, also have to shrink accordingly. And here, lithography tools play the crucial role.
As you can see from the roadmap, we've gone from 40nm metal pitch now down to 20nm, and we will scale even beyond that in CFET nodes. And that's quite aggressive scaling. To achieve that, the industry developed a new generation of lithography tool, so-called High NA EUV tool, with a numerical aperture of 0.55. And this gives us higher resolution. Basically, it helps us print tiniest features on wafers more precisely. And the good news, ASML has already built this machine, and it works. So, from manufacturing point of view, lithography is no longer the risk on this roadmap.
You actually very well see how the progress in lithography tools allows us to scale the metal pitch and unlock new levels. In fact, it mostly helps us to scale the metal pitch and not so much in the logic side, and many people miss that piece of the puzzle. And the numbers here, 0.33, 0.55, 0.75, refer to numerical aperture. The bigger number, the better, because it means better resolution and printing even smaller features on the wafer.
According to this roadmap, the older generation of lithography tools enables us scaling down to 22nm metal pitch. And below that, we're going to switch to the new generation 0.55 NA EUV tool. And at some point, this one will be no longer enough, and we will have to switch to the next generation of lithography tools, so-called Hyper Extreme EUV, which literally stands for hyper extreme extreme ultraviolet lithography. And this will unlock the next big milestone in semiconductors: 2D FET. Basically, it's the same vertical structure, but with 2D materials in the channel. So, now in the channel, we will have material just one atom thick.
What's interesting, right now it looks like 2D materials is the end game in semiconductors. And I talk a lot about new materials on this channel because in the last decades, what we've seen the most of advances were coming from new architectures, new lithography tools, new processes, but using the same silicon technology. But in the next decades, the real breakthroughs will be coming from new materials, those beyond silicon.
At the moment, it seems like two most promising materials are molybdenum disulfide (MoS2) and tungsten disulfide (WS2). The trick is that building them at scale is really hard because these are 2D materials, and they are by definition just one atom thick. And that makes them very tricky to work with in manufacturing. Remember a few moments ago, we discussed that we need to wrap the gate around the channel, which was very nicely done in Gate-All-Around technology. But when our channel becomes one atom thick, like a sheet of paper, there is not much material to wrap around. And on top of this, these thin layers are very fragile. So, even a tiny misalignment in manufacturing can cause them to break. And this is one big open challenge in manufacturing.
In fact, it's not one specific step that's causing the problem, but it's how all these steps fit together. Here, we have insanely small aspect ratios and trying to contact both transistors from top and the bottom separately, and then connecting power from the backside. And you have to do all of this with Ångström level precision, that's less than a nm. Imagine building a skyscraper out of Lego blocks, but each of your Lego block is the size of a grain of dust, and then you have to align them perfectly in an Ångström precision scale without even touching them. That's how precise advanced chip manufacturing has become.
The transition from FinFET to Gate-All-Around was a huge leap, but the transition from Gate-All-Around to CFET is going to be even a bigger one, especially when it comes to manufacturing complexity. Another promising material to keep an eye on are CNTs, and these are being actively explored by IMEC and TSMC. These CNTs are essentially rolled up sheets of graphene. And if you watch this channel regularly, you're already an expert on graphene. If not, make sure to subscribe right now to stay in the loop.
Graphene is certainly less mature compared to all other technologies we've discussed today, but it's very attractive for the post-silicon era because mostly because of its high speed and current at low voltages, which in practice means better power efficiency. Ideally, with graphene, we could go below today's 7 volt down to 0.5 volt or even lower power supply. And this would drastically cut power consumption because power scales is a square of the voltage. But here is a catch: while CNTs turn on very well, it's really hard to turn them off, meaning they leak power when they're idle. And that's a big problem, and we will have to find a way around it.
Now, the most likely scenario, instead of replacing all our devices in the chip with CNTs, first we will replace a particular part of the logic on the chip. And this is the key idea behind this new concept of CMOS 2.0, a new way of building chips in which we divide a chip into different layers, kind of a sandwich, where each layer has a specific job. Here, different technologies will be used for different layers or functions. Instead of cramming everything into one flat chip like we've done for decades, we can use the best material and technology for each layer. For example, one for AI and another for graphics.
Now, when we talk about scaling chips, the most of attention goes towards compute, while in fact, memory is now becoming the biggest bottleneck in today's systems. We mostly use SRAM for cache, DRAM for working memory, and NAND for storage. The tricky part is SRAM because it sits on the computing die and it's also made out of transistors, but it doesn't scale that well with new architectures. For example, with Gate-All-Around, as we move towards 3nm and 2nm, all the logic scales except the memory, and that's frustrating. And actually, what we see happening with every generation, memory on the memory eats up more and more area of the chip.
I've got some great news because actually the only architecture that really helps here is CFET, where you stack transistors vertically. That one actually fits SRAM layout very well and finally gives us a decent jump in density. DRAM, on the other hand, does keep scaling, but slowly. And now we are starting to go 3D, stacking layers of DRAM on top of each other. But here is the real issue: as compute becoming better with clever designs, advanced algorithms, and software, memory is not optimized this way. And so, we are hitting the memory wall. And if compute performance is keep improving, memory remains slow, power hungry part, especially for AI compute applications. And that's the next frontier we have to address.
So, what all of this means for NVIDIA and what it means for you? As chip manufacturing becoming more complex and more advanced, it will also become more expensive. While the cost of transistor may stay flat thanks to better density, the total cost of making a wafer skyrockets due to this complexity. It's also important that TSMC remains not the only player in this game. And Samsung and Intel are also heavily investing in the next gen manufacturing because we need healthy competition here, otherwise progress slows down. And these companies have to invest heavily into R&D just to stay competitive. That means cheap prices will likely go up, and so will the price of devices and the AI services built on top of them.
But if you're an investor, these are actually great news because more complexity means more opportunity. And right now, semiconductors is some of the high growth spaces out there. And my startup is actually in this space. Now, if you're looking at this from investment angle, here are a few players to keep an eye on: First of all, TSMC, the manufacturing leader. ASML, the only company that making EUV lithography machines. And Applied Materials, providing tools used in pretty much every step in the chip manufacturing process. And I don't mention IMEC here because they are nonprofit research institution.
So, if you enjoyed this episode, make sure to share it on LinkedIn, Instagram, or X, and make sure to tag me so I can see your posts. Thank you so much for watching. Love you guys. See you in the next one. Ciao.